1. Field of the Invention
The present invention relates to the field of semiconductor processing and more particularly to methods of forming of nickel sulfide film on semiconductor devices.
2. Discussion of Related Art
Low resistance contact layers are commonly formed on source/drain regions of transistors to improve performance, such as lowering the parasitic resistance. An example of a low resistance contact layer is the self-aligned silicide layer, commonly referred to as salicide. Current metal deposition for salicide formation is accomplished by physical vapor deposition (PVD). However, the directional nature of the depositing flux in the PVD technique has certain drawbacks, such as difficulty in depositing metal at the bottom of high aspect ratio features and non-conformal metal deposition on three-dimensional (3D) features of 3D transistor structures.
FIG. 1 illustrates an example of a 3D transistor structure known as the tri-gate transistor. The tri-gate transistor comprises a semiconductor body 30 having a fin shape formed on a substrate 40. Source/drain regions 31 are formed adjacent to opposite ends of the semiconductor body 30. A gate dielectric 50 is formed conformally onto the channel region 33, wherein channel region 33 refers to the portion between the source and drain regions 31. A gate electrode 60 is formed on the gate dielectric 50. The semiconductor body 30 can be doped to form source/drain regions 31. During doping of source/drain regions, the gate electrode 60 acts as a mask to prevent the channel region 33 from being doped.
FIG. 2A shows the cross-sectional view of the semiconductor body 30 across line A-A in FIG. 1, which also represents the source/drain region 31. Semiconductor body 30 is a fin-shaped or ridge-shaped structure comprising a top surface 71, a first sidewall 72 and a second sidewall 73, wherein the first and second sidewalls 72, 73 extend from opposite sides of the top surface 71 of source/drain region 31 to the top surface 41 of the substrate 40.
Typically, a PVD metal deposition is used to form contact layers on the tri-gate transistor. FIG. 2B illustrates a metal contact layer 80 formed on the semiconductor body 30 as well as the top surface of the substrate 40 by using a conventional PVD metal deposition. However, due to the directional nature of the depositing flux, the metal contact layer 80 is not formed conformally on the top surface 71 and sidewalls 72, 73. Next, in FIG. 2C, an annealing process following the PVD metal deposition usually results in non-uniform reaction between the metal contact layer 80 and the semiconductor body 30. The annealing process could cause excessive consumption 90 of the semiconductor body 30 by the metal contact layer 80.